The Background described in this section is included merely to present a general context of the disclosure. The Background description is not prior art to the claims in this application, and is not admitted to be prior art by inclusion in this section.
With ever-increasing memory bus speeds and tighter timing margins that must be achieved in cost-sensitive memory applications, optimal memory timing parameters can be crucial for design and implementation. Most memory controller and physical transceivers offer timing parameter adjustability to compensate for process variations (i.e., semiconductor skew), temperature ranges, board-level variations, voltage levels, and memory devices from different manufacturers. Additionally, with the trend toward SoC (system-on-chip) where a DRAM die is integrated into the chip package, the largest possible timing margin window is needed for each design to avoid yield and reliability issues. Often, simulations can only accurately account for some of these variables, and implementations may not meet expected simulation results, such as when temperature and voltage differences are encountered after products are delivered for customer implementation.